1. Field of the Invention
The field of the present invention generally relates to electronic design automation and testing of integrated circuits, and, more particularly, to methods and systems for testing embedded cores in complex, multi-core integrated circuit designs.
2. Background
Chip designers often use electronic design automation (EDA) software tools to assist in the design process, and to allow simulation of a chip design prior to prototyping or production. Chip design using EDA software tools generally involves an iterative process whereby the chip design is gradually perfected. Typically, the chip designer builds up a circuit by inputting information at a computer workstation generally having high quality graphics capability so as to display portions of the circuit design as needed. A top-down design methodology is commonly employed using hardware description languages (HDLs), such as Verilog(copyright) or VHDL, for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the circuit, and then decomposing each component into smaller and smaller components.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then xe2x80x9cplacedxe2x80x9d (i.e., given specific coordinate locations in the circuit layout) and xe2x80x9croutedxe2x80x9d (i.e., wired or connected together according to the designer""s circuit definitions) using specialized placement and routing software, resulting in a physical layout file. A mask file, for example a GDSII or CIF format, may be provided to a foundry, and contains enough information to allow the foundry to manufacture an actual integrated circuit therefrom.
At various stages of the design process, validation of the design may be desired through test or verification procedures. To test a design, a set of test vectors is ordinarily generated which will be applied to the inputs to the design and compared against the outputs of the design. An error in the design will be indicated if the actual output generated by the design does not match the expected output. A test access port (TAP) is usually provided on-chip for receiving input test data from a test data source and outputting output test data from the integrated circuit. The test access port is generally used for testing an integrated circuit during and after the manufacturing of the integrated circuit. Another common use of the test access port is on a printed circuit board (PCB) where interconnectivity between multiple components (ICs) can be verified in addition to testing the individual components (ICs). The test access port is generally connected to a serially linked set of boundary-scan cells, one such cell for each input and output pin of the integrated circuit. The test access port controls the inflow and outflow of information with respect to the boundary-scan cells, and hence with respect to the integrated circuit core.
Test and verification processes are facing new challenges due to changes in integrated circuit (IC) design. In particular, decreases in the feature size of circuit elements has led to the ability to place more components on a single integrated circuit. At the same time, decreases in design cycle time are being sought, in order to allow faster time-to-market and hence a potential competitive advantage. Due in part to these trends, the current trend in integrated circuit core design is to create more and more complex cores capable of being stored on a single IC. Design cores that were previously whole ICs have now been reduced to sizes allowing their use as individual components of complex ICs containing multiple design cores.
Another trend in the integrated circuit design industry is to reuse pre-existing circuit blocks in a new design, particularly in multi-core integrated circuits, in order to reduce the development time of an integrated circuit. The pre-existing circuit blocks may be xe2x80x9csoftxe2x80x9d or xe2x80x9chardxe2x80x9d, or somewhere in between. A xe2x80x9csoftxe2x80x9d circuit block is one that has not been physically laid out, while a xe2x80x9chardxe2x80x9d circuit block has its physical layout already determined (i.e., placement and routing of its internal components has been achieved). Pre-existing circuit blocks may occasionally be referred to as xe2x80x9cVCsxe2x80x9d (short for xe2x80x9cVirtual Componentsxe2x80x9d) or xe2x80x9cIPsxe2x80x9d (short for xe2x80x9cIntellectual Properties,xe2x80x9d suggesting their proprietary nature to particular designers). Often, pre-existing circuit blocks will include their own individual test access port to allow testing of the IP itself, assuming the test access port is accessible through chip-level pins after the pre-existing circuit block is placed in a larger integrated circuit design.
The state-of-the-art approach to complex IC design involves system development using pre-existing circuit cores (e.g., VCs or IPs) which have already been individually tested using manufacturer developed test vectors. Often, a basic IC platform is developed, and as the design functionality is expanded more pre-existing circuit cores are added to the hierarchy of the design. Reuse of pre-existing integrated circuit cores generally raises the possibility of using the existing manufacturing level test vectors to further reduce total design and verification time. Investing time in developing new test vectors when test vectors already exist for a given virtual component block would defeat the goal of reducing the time-to-market through partial design reuse. This is particularly true if the reused virtual component block is already hardened, leaving little or no room to generate different test vectors.
As the design size and complexity of integrated circuits has increased, the time necessary to develop manufacturing level test vectors has also increased significantly, causing increased delays in delivering the chips to market. To complicate matters further, the widely accepted IC test standard, Standard 1149.1 promulgated by the Institute of Electrical and Electronics Engineers (IEEE), cannot be used directly in ICs containing embedded cores with built-in test access ports. The 1149.1 standard was formulated with the goal of allowing one test access port per chip, and does not take into account the possibility of chip designs containing multiple embedded cores, some of which may already have built-in 1149.1 compliant test access ports. This problem is becoming increasingly significant as the 1149.1 test standard has reached widespread acceptance in the electronics and semiconductor industries, making it highly desirable that current and future ICs be fully compliant with the standard.
Use of existing or even new test vectors to test the individual cores inside multi-core integrated circuits poses difficult challenges because the individual cores are embedded within the chip, with limited or no direct pin access exterior to the chip itself. When the multi-core integrated circuits are manufactured, only necessary external connectivity is maintained; therefore, many of the pins of the of the individual circuit blocks are partially or completely inaccessible from outside the chip. Because external connectivity to each pin of the individual circuit blocks cannot be provided, testing individual circuit blocks by applying a set of test vectors to the manufactured multi-core integrated circuit designs can be problematic. Further, even if the circuit blocks have boundary-scan (BS) ports, and even if the test vectors are designed to test the individual circuit blocks through their boundary-scan ports, it is neither feasible nor efficient to bring the connectivity of the entire boundary-scan port of all such circuit blocks out to the edge of the chip because this would significantly increase the number of test pins at the chip level.
Various methodologies have recently been proposed to address the difficulties associated with testing the embedded cores in complex ICs while still adhering to the IEEE 1149.1 standard. One approach, for example, is described in Lee Whetsel, xe2x80x9cAn IEEE 1149.1 Based Test Access Architecture for ICs With Embedded Cores,xe2x80x9d Proc. International Test Conference, 1997, pp. 69-78, hereby incorporated by reference as if set forth fully herein. The approach detailed in this article, while directed to the problems associated with testing embedded IC cores, requires modification to the existing test access port (TAP) controllers in the circuit blocks, including a large amount of logic (resulting in modified TAP controllers) at each level of core hierarchy. Other methodologies not requiring modifications to existing test access port controllers, and directed primarily to designs having pre-hardened blocks, may require the addition of a modified TAP controller (known as an HTAP) at each circuit block hierarchy level. Such an approach is described in D. Bhattacharya, xe2x80x9cHierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit,xe2x80x9d Proc. VLSI Test Symposium, 16th IEEE, 1998, pp. 8-14, hereby incorporated by reference as if set forth fully herein. The aforementioned conventional approaches may require increased engineering time and effort, due to the complexity of the implementation involved, and may further require specialized software tools.
Another method for testing embedded cores in complex ICs makes use of multiplexers (MUXs) to select a desired circuit block containing the core to be tested. With this approach, the number of select pins needed for multiplexing is generally log2N, rounded up, where N is the number of embedded cores to be tested in the design. Thus, for example, four select pins would be necessary to select one of nine circuit blocks containing an embedded core within a chip, since log29 rounded up is 4. While allowing access to different embedded cores, this technique can be undesirable because it requires a number of chip test pins proportional to the number of cores embedded in the integrated circuit, which becomes inefficient for complex designs containing large numbers of embedded cores.
A need thus exists for a scaleable, efficient mechanism to access embedded cores for testing in complex ICs, particularly one that is compatible with the IEEE 1149.1 standard, that requires minimal design and area overhead, and that interfaces easily with pre-existing individual circuit blocks having standard test access port interfaces (without requiring any modifications to the existing circuit blocks). A need further exists for a technique to test reused or derivative designs which are connected in a hierarchy, without requiring modification of the pre-existing designs or test vectors.
The invention provides in one aspect a method and system for testing multiple-core integrated circuits that can be compatible with the IEEE 1149.1 standard test access port of each circuit block containing an internal core.
In one embodiment as disclosed herein, a system and method are provided for testing an integrated circuit comprising one or more circuit blocks, each containing an internal core, and a test access port (e.g., an IEEE standard 1149.1 compliant test access port) preferably connected to a set of boundary-scan cells. A Select Register (preferably a serial register) is added to the integrated circuit, the purpose of which is to receive and hold the address of a circuit block to be accessed in order to test the internal core of the circuit block. Each circuit block is preferably assigned a unique address. One or more demultiplexers are added to the integrated circuit to provide an interface between input test access port signals and the various individual circuit blocks, and one or more multiplexers are added to the integrated circuit to provide an interface between the various individual circuit blocks and the output test access port signals. The address bits read into the Select Register act as the select signal(s) for the one or more demultiplexers and multiplexers. In response to the select signal(s) (i.e., the address bits), the input test access port signals are selectively routed (via the demultiplexer(s)) to the circuit block having the appropriate address, and output signals from the same circuit block are selected (via the multiplexer(s)), from among the output signals of all of the circuit blocks, as output test access port signals. By changing the address in the Select Register, the internal cores of the individual circuit blocks within the overall integrated circuit design can be systematically selected for testing.
In another embodiment, the above technique is expanded for use in a hierarchical integrated circuit design, wherein circuit blocks are divided into groupings at different hierarchical levels. In this embodiment, multiple Select Registers are added to the integrated circuit, a Select Register at each level of the hierarchical design for each group of circuit blocks. At the highest or top-level hierarchy in an integrated circuit one or more demultiplexers are added to provide an interface between input Test Access Port signals and the various individual circuit blocks or lower-level hierarchies, and one or more multiplexers are added to provide an interface between the various individual circuit blocks or lower-level hierarchies and the output Test Access Port signals. Similarly, at the lower hierarchical levels, one or more demultiplexers are added to provide an interface between lower-level Test Access Port input signals and the lower-level circuit blocks, thereby allowing the output (or outputs) of the top-level demultiplexer (or demultiplexers) to reach the various individual circuit blocks or next lower-level hierarchy. One or more multiplexers are also added at the lower-level hierarchies to provide an interface between the lower-level circuit blocks or the next lower-level hierarchy and lower-level Test Access Port output signals, thereby allowing the output (or outputs) of the lower-level circuit blocks or lower-level hierarchies to reach input (or inputs) of the top-level multiplexer (or multiplexers). In this embodiment, the address bits read into the top-level Select Register act as the select signal(s) for the one or more top-level demultiplexers and multiplexers, and the address bits are passed through from the top-level Select Register to the lower-level Select Register(s) so that the proper lower-level circuit block or next lower-level hierarchy can also be selected. In response to the select signal(s) (i.e., the address bits), the input Test Access Port signals are selectively routed via the top-level and/or lower-level demultiplexers to the circuit block at the designated hierarchical level having the designated address. Output signals from the same circuit block are also simultaneously selected as output Test Access Port signals (via the lower-level and/or top-level multiplexers) from among the output signals of all the circuit blocks. By changing the address in the top-level and/or lower-level Select Registers, the internal cores of the individual circuit blocks within the overall integrated circuit design can be systematically selected for testing.
In certain embodiments, the internal core of any circuit block or multiple circuit blocks embedded in an integrated circuit or chip may be selected for testing by loading the corresponding address bits of the circuit block containing the core into the Select Register (or Select Registers). To test the selected core, test vectors may be scanned into the boundary-scan registers of the internal core. The test stimuli are applied in parallel to the selected core, and the response of the internal core is captured in parallel by the appropriate boundary-scan registers and scanned out through the test access port for test analysis.
In various embodiments, all bits of the Select Register(s) can be cleared either by a system power-up or by a Test Reset signal, causing the highest level circuit block (in a hierarchical test structure) to become the selected default. In other embodiments, the Test Reset signal to the Select Registers can be omitted in order to prevent the Select Register(s) from being reinitialized during power up, leaving the Select Register(s) with an undetermined value at initial state. A known data value can then be moved into the circuit block Select Register at a later time in order to select a circuit block for testing. Omitting the test reset event prior to loading the address bits of a new circuit block also allows the state of the currently selected circuit block to be maintained in the Select Register by not forcing the Select Register to reset state, which is useful during interconnectivity testing between multiple cores within a chip.
In certain embodiments, hierarchical addressing allows any selected circuit block to be reset using the Test Mode Select and Test Clock signals. In a preferred embodiment, only the test access port of a selected circuit block will receive such a reset sequence, in the same manner that only selected test access ports receive test vectors. The reset generated using the Test Mode Select and Test Clock signals will not modify the current status of any circuit block other than the circuit block corresponding to the selected address bits. Interconnectivity testing between multiple circuit blocks within a single circuit chip can be accomplished by allowing the Select Registers to be loaded with a new value without modifying the current status of the previously selected circuit block. This allows a currently selected circuit block to be programmed to drive certain values on selected pins of the circuit block, and a new address can optionally be loaded into the Select Registers to select a different circuit block without affecting the state of the currently selected circuit block.
In some embodiments, the Test Reset signal can also be demultiplexed in the same manner as the Test Clock signal, allowing a top-level reset operation to reset only the selected circuit block without resetting any other circuit block in the chip. A reset sequence is sent only to the circuit block corresponding to the address bits of the Select Register, rather than performing a chip-level rest sequence which would reset all circuit blocks of the chip.
In some embodiments, a power-up reset circuit can be used to ensure that the chip-level test access port is selected when a reset sequence is performed after power-up, rather than the circuit block corresponding to the address bits in the Select Register. This is desirable because the contents of the Select Registers (and hence the circuit block selection) may be undetermined at the time of power-up. Among other things, such embodiments provide the flexibility of resetting any given circuit block without affecting the rest of the circuit blocks in the chip.